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E2U0021-28-81
Semiconductor MSM7704-01/02/03
Semiconductor 2ch Single Rail CODEC
This version: Aug. 1998 MSM7704-01/02/03 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7704-01/7704-02/7704-03 are two-channel CODEC CMOS ICs for voice signals ranging from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, these devices contain two-channel AD/DA converters in a single chip and achieve a reduced footprint and a reduced number of external components. The MSM7704-01/7704-02/7704-03 are best suited for an analog interface to an echo canceller DSP used in digital telephone terminals, digital PABXs, and hands free terminals.
FEATURES
* Single power supply: +2.7 V to +3.8 V * Power consumption Operating mode: 30 mW Typ. 50 mW Max. Power-saving mode: 3 mW Typ. 6 mW Max. Power-down mode: 0.03 mW Typ. 0.3 mW Max. * ITU-T Companding law MSM7704-01: m/A-law pin-selectable MSM7704-02: m-law MSM7704-03: A-law * Built-in PLL eliminates a master clock * The PCM interface can be switched between 2 channel serial/parallel * Transmission clock: 64/128/256/512/1024/2048 kHz 96/192/384/768/1536/1544/200 kHz (During 2 channel serial mode, the 64 and 96 kHz clocks are disabled) * Adjustable transmit gain * Built-in reference voltage supply * Analog output can directly drive a 1.2 kW load * Package: 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7704-01GS-K) (Product name : MSM7704-02GS-K) (Product name : MSM7704-03GS-K)
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BLOCK DIAGRAM
AIN1 GSX1 AIN2 GSX2
- +
RC LPF
8th BPF
AD CONV.
DOUT1 DOUT2 TCONT
- +
RC LPF
8th BPF AUTO ZERO
PLL
XSYNC BCLK
AOUT1
- +
5th LPF
RTIM S&H DA CONV.
RSYNC (ALAW)
AOUT2
- +
5th LPF
S&H
RCONT
CHPS DIN1 DIN2 PDN VDD AG DG
SGC
SG GEN
VR GEN
PWD Logic
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PIN CONFIGURATION (TOP VIEW)
SGC 1 AOUT2 2 NC 3 AOUT1 4 PDN 5 CHPS 6 NC 7 VDD 8 DG 9 RSYNC 10 DIN2 11 DIN1 12
24 AIN2 23 GSX2 22 GSX1 21 AIN1 20 NC 19 (ALAW)* 18 AG 17 NC 16 BCLK 15 XSYNC 14 DOUT2 13 DOUT1
NC : No connect pin 24-Pin Plastic SOP
* The ALAW pin is only applied to the MSM7704-01GS-K.
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PIN AND FUNCTIONAL DESCRIPTIONS
AIN1, AIN2, GSX1, GSX2 AIN1 and AIN2 are the transmit analog inputs for channels 1 and 2. GSX1 and GSX2 are the transmit level adjustments for channels 1 and 2. AIN1 and AIN2 are inverting inputs for the op-amps. GSX1 and GSX2 are connected to the outputs of the op-amps and are used to adjust the level, as shown below. When AIN1 and AIN2 are not used, connect AIN1 to GSX1 and AIN2 to GSX2. During power saving mode and power down mode, the GSX1 and GSX2 outputs are in high impedance state.
R2 CH1 Analog Input C1 R1
GSX1 AIN1 - +
CH1 Gain Gain = R2/R1 10 R1: Variable R2 > 20 kW C1 > 1/(2 3.14 30 R1)
R4 CH2 Analog Input C2 R3
GSX2 AIN2 - +
CH2 Gain Gain = R4/R3 10 R3: Variable R4 > 20 kW C2 > 1/(2 3.14 30 R3)
AOUT1, AOUT2 AOUT1 is the receive analog output for channel 1 and AOUT2 is used for channel 2. The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage (SG : 1/2 VDD). When the digital signal of +3 dBmO is input to DIN1 and DIN2, it can drive a load of 1.2 kW or more. During power saving mode, or power down mode, these outputs are at the voltage level of SG with a high impedance. VDD Power supply for +3 V. A power supply for an analog circuit in the system to which the device is applied should be used. A bypass capacitor of 0.1 mF to 1 mF with excellent high-frequency characteristics and a capacitor of 10 mF to 20 mF should be connected between this pin and the AG pin if needed.
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Semiconductor DIN1
MSM7704-01/02/03
PCM signal input for channel 1 when the parallel mode is selected. D/A conversion is performed with the serial PCM signal input to this pin, the RSYNC signal synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is output from AOUT1 pin. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is not used and should be connected to GND (0 V). DIN2 PCM signal input for channel 2 when the parallel mode is selected. D/A conversion is performed with the serial PCM signal input to this pin, the RSYNC signal synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is output from AOUT2 pin. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is used for the 2ch multiplexed PCM signal input. BCLK Shift clock signal input for the DIN1, DIN2, DOUT1, and DOUT2 signals. The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048, or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. RSYNC Receive synchronizing signal input. Eight bits PCM data required are selected from a series of PCM signal to the DIN1 and DIN2 pins by the receive synchronizing signal. All timing signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK (generated from the same clock source as BCLK). The frequency should be 8 kHz 50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the receive section. However, unless the frequency characteristics of the system used are strictly specified, this device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics specified in the data sheet are not guaranteed.
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MSM7704-01/02/03
Transmit synchronizing signal input. PCM output signal from the DOUT1 and DOUT2 pins is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK. The frequency should be 8 kHz 50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the transmit section. However, unless the frequency characteristics of the system used are strictly specified, this device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to power saving state. DOUT1 PCM signal output of channel 1 when the parallel mode is selected. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down state. When the serial mode is selected, this pin is configured to be the output of serial multiplexed 2ch PCM signal. A pull-up resistor must be connected to this pin because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7704-03 (A-law) outputs the character signal, inverting the even bits.
PCMIN/PCMOUT MSM7704-02 (m-law) MSD +Full scale +0 -0 -Full scale 1000 1111 0111 0000 0000 1111 1111 0000 MSM7704-03 (A-law) MSD 1010 1101 0101 0010 1010 0101 0101 1010
Input/Output Level
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DOUT2 PCM signal output for channel 2 when the parallel mode is selected. The PCM output signal is output from MSD in a sequential order, at the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down state. When the serial mode is selected, this pin is left open. A pull-up resistor must be connected to this pin because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7704-03 (A-law) outputs the character signal inverting the even bits. CHPS Control signal input for the mode selection of PCM input and output. When this signal is at a logic "1" level, the PCM input and output are in the parallel mode. The PCM data of CH1 and CH2 is input to DIN1 and DIN2 and output from DOUT1 and DOUT2 with the same timing. When this signal is at a logic "0" level, the PCM input and output are in the serial mode. The PCM data of CH1 and CH2 is input to DIN2 and output from DOUT1 as time division multiplexed data. The parallel mode is conveniently applied to the digital interface to the echo canceller device, and the serial mode is applied to the digital interface to PCM multiplexer's for PABXs. PDN Power down control signal. When PDN is at a logic "0" level, both transmit and receive circuits are in power down state. AG Analog signal ground. DG Ground for the digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground.
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Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. ALAW Control signal input of the companding law selection. Provides only for the MSM7704-01GS-K. The CODEC will operate in the m-law when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since this pin is internally pulled down.
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition
-- -- -- --
Rating 0 to 7 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -55 to +150
Unit V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Analog Input Voltage Digital Input High Voltage Digital Input Low Voltage Symbol VDD Ta VAIN VIH VIL Gain = 1 XSYNC, RSYNC, BCLK, DIN1, DIN2, PDN, CHPS Condition Voltage must be fixed
--
Min. 2.7 -30 -- 0.45 VDD 0
Typ. 3.0 +25 -- -- --
Max. 3.8 +85 1.4 VDD 0.16 VDD
Unit V C VPP V V
Clock Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time Sync Pulse Width DIN Set-up Time DIN Hold Time Digital Output Load Analog Input Allowable DC Offset Allowable Jitter Width
FC FS DC tIr tIf tXS tSX tRS tSR tWS tDS tDH RDL CDL Voff --
BCLK = (eliminates 64, 96 kHz, when 2ch serial mode) XSYNC, RSYNC BCLK XSYNC, RSYNC, BCLK, DIN1, DIN2, PDN, CHPS
BCLKAEXSYNC, See Timing Diagram XSYNCAEBCLK, See Timing Diagram BCLKAERSYNC, See Timing Diagram RSYNCAEBCLK, See Timing Diagram
64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, 1536, 1544, 200 -- 40 -- -- 100 100 100 100 1 BCLK 100 100 0.5 -- 8.0 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60 50 50 -- -- -- -- 100 -- -- -- 100 VDD/2 +100 VDD/2 +10 500 kHz % ns ns ns ns ns ns ms ns ns kW pF mV mV ns kHz
XSYNC, RSYNC DIN1, DIN2 DIN1, DIN2 Pull-up resistor, DOUT1, DOUT2 DOUT1, DOUT2
Transmit gain stage, Gain = 1 VDD/2 -100 Transmit gain stage, Gain = 10 VDD/2 -10 XSYNC, RSYNC --
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ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 2.7 V to 3.8 V, Ta = -30C to +85C) Parameter Symbol IDD1 IDD2 Condition Operating mode, No signal Power-save mode, PDN = 1, Power Supply Current XSYNC or BCLK OFF Power-down mode, PDN = 0 Digital input is at 0 V -- -- -- -- Pull-up resistance > 500 W -- -- -- 1.0 4.0 mA Min. -- Typ. 10.0 Max. 14.0 Unit mA
IDD3 Input High Voltage Input Low Voltage High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output Leakage Current Input Capacitance VIH VIL IIH IIL VOL IO CIN
-- 0.45 VDD 0.0 -- -- 0.0 -- --
0.01 -- -- -- -- 0.2 -- 5
0.05 VDD 0.16 VDD 2.0 0.5 0.4 10 --
mA V V mA mA V mA pF
Transmit Analog Interface Characteristics
(VDD = 2.7 V to 3.8 V, Ta = -30C to +85C) Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RINX RLGX CLGX VOGX VOSGX Gain = 1 Condition AIN1, AIN2 GSX1, GSX2 with respect to SG Min. 10 20 -- -0.7 -20 Typ. -- -- -- -- -- Max. -- -- 30 +0.7 +20 Unit MW kW pF V mV
Receive Analog Interface Characteristics
(VDD = 2.7 V to 3.8 V, Ta = -30C to +85C) Parameter Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RLAO CLAO VOAO VOSAO Condition AOUT1, AOUT2 (each) with respect to SG AOUT1, AOUT2 AOUT1, AOUT2, RL = 1.2 kW with respect to SG AOUT1, AOUT2 with respect to SG Min. 1.2 -- -1 -100 Typ. -- -- -- -- Max. -- 50 +1 +100 Unit kW pF V mV
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Semiconductor AC Characteristics
MSM7704-01/02/03
(VDD = 2.7 V to 3.8 V, Ta = -30C to +85C) Parameter Symbol Loss T1 Loss T2 Transmit Frequency Response Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Loss R2 Receive Frequency Response Loss R3 Loss R4 Loss R5 SD T1 SD T2 Transmit Signal to Distortion Ratio SD T3 SD T4 SD T5 SD R1 SD R2 Receive Signal to Distortion Ratio SD R3 SD R4 SD R5 GT T1 GT T2 Transmit Gain Tracking GT T3 GT T4 GT T5 GT R1 GT R2 Receive Gain Tracking GT R3 GT R4 GT R5 1020 1020 1020 1020 Freq. (Hz) 60 300 1020 2020 3000 3400 300 1020 2020 3000 3400 3 0 -30 -40 -45 3 0 -30 -40 -45 3 -10 -40 -50 -55 3 -10 -40 -50 -55 *2 *2 -0.4 -1.0 -1.2 -0.3 -0.5 -1.2 -0.3 *1 *1 0 -0.15 -0.15 0.0 35 35 35 28 23 36 36 36 30 25 -0.3 0 Level Condition (dBm0) Min. 20 -0.15 -0.15 -0.15 0 -0.15 Typ. 26 +0.07 Reference -0.04 +0.06 0.4 -0.03 Reference +0.02 +0.12 0.46 43 41 38 31.5 27 43 41 40 33.5 30 +0.01 Reference 0 -0.03 -0.05 -0.06 Reference +0.2 +0.62 +0.20 +0.65 +0.3 +0.4 +1.0 +1.2 dB +0.3 +0.5 +1.2 +0.3 dB +0.20 +0.20 0.80 -- -- -- -- -- -- -- -- -- -- +0.3 dB dB +0.20 +0.20 0.80 +0.20 Max. -- +0.20 Unit dB dB dB dB dB dB dB dB dB dB dB
*1 Psophometric filter is used *2 Upper is specified for the m-law, lower for the A-law
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Semiconductor AC Characteristics (Continued)
MSM7704-01/02/03
(VDD =2.7 V to 3.8 V, Ta = -30C to +85C) Parameter Symbol Nidle T Nidle R AV T Absolute Level (Initial Difference) AV R AV Tt AV Rt 1020 0 Freq. (Hz) -- -- Level Condition (dBm0) AIN = SG -- *1 *2 -- *1 *3 VDD = 3.0 V Ta = 25C *4 VDD = 2.7 V to 3.8 V Ta = -30 to +85C *4 A to A Absolute Delay Td tgd T1 tgd T2 Transmit Group Delay tgd T3 tgd T4 tgd T5 tgd R1 tgd R2 Receive Group Delay tgd R3 tgd R4 tgd R5 CR T Crosstalk Attenuation CR R CR CH 1020 0 1020 500 600 1000 2600 2800 500 600 1000 2600 2800
TRANS AE RECV RECV AE TRANS
Min. -- -- 0.338 0.483 -0.2 -0.2
Typ. -73.5 -71.5 -76 0.350 0.500 -- --
Max. -69 -68 -74 0.362
Unit
Idle Channel Noise
dBmOp
Vrms 0.518 +0.2 +0.2 dB dB
Absolute Level (Deviation of Temperature and Power)
0
BCLK = 64 kHz *5
-- -- -- -- -- -- *5 -- -- -- -- -- 75 70 75
-- 0.19 0.11 0.02 0.05 0.07 0.00 0.00 0.00 0.09 0.12 80 76 80
0.60 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 -- -- --
ms
0
ms
0
ms
dB
CH to CH
*1 *2 *3 *4 *5
Psophometric filter is used Upper is specified for the m-law, lower for the A-law Input "0" code to PCMIN AVT is defined between GSX and DOUT and AVR between DIN and AOUT Minimum value of the group delay distortion
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Semiconductor AC Characteristics (Continued)
MSM7704-01/02/03
(VDD = 2.7 V to 3.8 V, Ta = -30C to +85C) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Symbol Freq. Level Condition (Hz) (dBm0) 4.6 kHz to 0 to 0 DIS 72 kHz 4000 Hz S IMD PSR T PSR R tSD Digital Output Delay Time tXD1 tXD2 tXD3 CL = 100 pF + 1 LSTTL 300 to 3400 fa = 470 fb = 320 0 to 50 kHz 0 -4 50 mVPP 4.6 kHz to 100 kHz 2fa - fb *6 Min. 30 -- -- -- 20 20 20 20 Typ. 32 -37.5 -52 30 -- -- -- -- Max. -- -35 -35 -- 200 200 200 200 ns Unit dB dBmO dBmO dB
*6 The measurement under idle channel noise
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Semiconductor
TIMING DIAGRAM
Transmit Timing
BCLK
tXS XSYNC
DOUT1 DOUT2
Receive Timing
BCLK
tRS RSYNC
DIN1 DIN2
BCLK XSYNC DOUT1
, ,
1 2 3 tSX tWS tXD1 tSD MSD D2 1 2 3 tSR tWS tDS MSD D2
MSD D2 D3 D4 D5 D6
MSM7704-01/02/03
4
5
6
7
8
9
10
11
tXD2 D3
D4
D5
D6
D7
tXD3 D8
Transmit Side
4
5
6
7
8
9
10
11
tDH D3 D4 D5 D6 D7 D8 Receive Side
Figure 1 Timing Diagram in the Parallel Mode (CHPS = 1)
D7
D8 MSD D2
D3
D4
D5
D6
D7
D8
CH1 PCM Data
CH2 PCM Data Transmit Side
BCLK RSYNC DIN2
MSD D2 D3 D4 D5 D6 D7 D8 MSD D2 D3 D4 D5 D6 D7 D8
CH1 PCM Data
CH2 PCM Data Receive Side
Figure 2 Timing Diagram in the Serial Mode (CHPS = 0)
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APPLICATION CIRCUIT
Example of Basic Connection (PCM Serial Mode Operation)
+3 V MSM7704 CH1 Analog Input CH1 Analog Output CH2 Analog Input CH2 Analog Output 0V +3 V 0 to 10 W 10 mF + 1 mF AIN1 GSX1 AOUT1 AIN2 GSX2 AOUT2 0.1 mF SGC AG DG DOUT1 DOUT2 DIN2 DIN1 BCLK XSYNC RSYNC PDN CHPS VDD 0V 1 kW 2ch Multiplex PCM (Open) Signal Output 0V 2ch Multiplex PCM Signal Intput Bit Clock Input Sync Pulse Input Power Down Control Input 1: Operation 0: Power Down
PCM Parallel Mode
MSM7704 CH1 Analog Input CH1 Analog Output CH2 Analog Input CH2 Analog Output 0.1 mF 0V +3 V 0 to 10W 10 mF + 1 mF AIN1 GSX1 AOUT1 DIN2 DIN1 AIN2 GSX2 AOUT2 SGC AG DG BCLK XSYNC RSYNC PDN CHPS VDD DOUT1 DOUT2
+3 V CH1 PCM Signal Output CH2 PCM Signal Output CH2 PCM Signal Input CH1 PCM Signal Input Bit Clock Input Sync Pulse Input Power Down Control Input 1 : Operation 0 : Power Down
+3 V
The AOUT1 and AOUT2 output signals swing 1.0 V above and below the offset level of VDD/ 2.
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RECOMMENDATIONS FOR ACTUAL DESIGN
* To assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. * Connect the AG pin and the DG pin each other as close as possible. Connect to the system ground with low impedance. * Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an IC socket is unavoidable, use the short lead type socket. * When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. * Keep the voltage on the VDD pin not lower than -0.3 V even instantaneously to avoid latchup phenomenon when turning the power on. * Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.
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PACKAGE DIMENSIONS
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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